Current campaign only (from 2026-10-18). Each workload: the HW is fitted to its ring-mapped traffic, mappings are re-searched on that HW, repeated until converged; speedup is against uniform HW with the best of every mapping type. Everything published before 2026-10-18 01:55 (per-workload graphs, ablation, forwarding sensitivity, fast-path groups) is in the Backup · asym study 2026-10-18 01:55 tab. Sections without new data stay empty until the campaign reaches them.
Goal: with the same total D2D capacity as uniform 256 B/cycle/link, find K=2 asymmetric tile designs that run faster on all 16 workloads (9 CNN, 2 RNN, 5 Transformer) at batches 1/4/16. Every source TX equals the adjacent RX, no boundary D2D port is left unconnected, rotations only. Speedup = (best uniform cycles / asymmetric cycles − 1) × 100%. The uniform side is the fastest native-validated uniform result from any study, and it always receives the same added mapping search.
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All methods extend Gemini's mapper (DP layer grouping + simulated-annealing spatial mapping). Each is a cumulative ablation level: a level's candidate pool is the union of every mapping found so far, re-evaluated on every K=2 width design, so a level only adds options. Figures use the C8 2×4 array; chip numbers follow the simulator.
With K=2 tiles, matched TX/RX and no reflection, C8 has exactly three width groups: c = one ring direction (“cw”, 8 links), a = the opposite ring direction (“ccw”, 8 links), b = middle cross links (4). 8a + 4b + 8c = 5120 B/cycle → 3,081 designs, all evaluated. Asymmetry pays off only if traffic prefers one ring direction.
Gemini’s search with chiplet-swap and tensor-order moves, plus coherent tensor-partition placement (a layer’s partitions stay chiplet-major). With default XY routing the traffic is direction-symmetric (Darknet19 b1: 61.3 MB vs 61.7 MB), so a ≈ c is selected and gains are small.
New SA move guided_ring_flow (48 options: direction × 8 ring offsets × mode). It lays consecutive pipeline stages along the ring (mode placement) and/or chooses DRAM read/write homes so that DRAM streams run in the ring direction (mode DRAM).
Gemini only routes XY. A transfer from chip 4 to chip 3 then uses four hops of the narrow direction; YX uses the wide ring. Each transfer takes whichever of XY/YX follows the chosen ring (source routing, independent of link widths). Darknet19 b1 traffic becomes 82 MB vs 26 MB, and c ≫ a designs start to win.
A multicast (e.g. one DRAM read broadcast to several chips) is forwarded destination-to-destination along the ring instead of a tree, so broadcast traffic also uses only the wide direction. Assumption: destination cores can forward; serial forwarding latency is not modeled by Gemini.
The SA mapper adapts to the HW it searches on. L4 repeats all searches on a second asymmetric HW; L5 searches again on the currently best widths and adds route scope (route choice on DRAM-only or core-only traffic); L6 searches every batch again on the workload’s best common HW, so a batch that loses there can get a mapping fitted to it (LSTM b16: −11.9% → +0.6%).
| Level | Method | Search variants (pool labels) |
|---|---|---|
| L0 | Baseline + coherent partition | baseline, partition |
| L1 | Ring-flow SA operator | ring |
| L2 | XY/YX route choice | routecw, ringcw |
| L3 | Multicast ring forwarding | chaincw, ringchaincw |
| L4 | Search-HW diversity (seed 2) | all of the above on a second HW |
| L5 | HW–mapping alternation + route scope (seed 3) | + scopedram, scopecore (C4 also chain λ variants) |
| L6 | Common-HW mapping alternation (seed 4) | all variants on the best common HW |
Each search also runs in three DP grouping modes (g1, hybrid, g4). Within K=2 the C8 family (a, b, c) and the C4 family (ax, ay, cx, cy; sum 1024) are the complete design spaces and are searched exhaustively.
Kept out of every mapping pool and selection (rule: no experiment that improves the uniform baseline).
| Method | Idea | Result (own cycles on the search HW) | Why rejected |
|---|---|---|---|
| λ route-cost variants (C8) | Partial steering: weight counter-ring hops by λ = 0.5 / 2. | GNMT b16 asym 27,236 vs best uniform 22,514 | No asymmetric gain. |
| L7 load-aware routing | Per transfer choose XY/YX/chain by (link load + bytes) / width. | Darknet19 b1 asym 22.7k–27.5k, uniform 30.9k (XY: ~20.7k) | Worse on both sides; loads seen while routing are partial (Gemini merges per-layer NoC objects later), and routing becomes order-dependent. |
| L7 width-ratio split | Each (src,dst) prefers cw with probability = cw-ring width share. | Darknet19 b1 uniform 16.2k (best so far 20.7k), asym 21.8k | Mainly speeds up the uniform baseline. |
| L8a traffic-class separation (C8) | DRAM flows steered to the wide ring; core flows cross on the middle links. | GNMT/LSTM/vgg19 b16 asym worse than before; darknet19 b4 uniform 35.1k (best so far 40.5k) | No asymmetric gain at b16; improves the uniform baseline at b4. |
| L8b ring rotation (NN-Baton style) | Read a tensor once and rotate it chip-to-chip along the wide ring. | Not run | Gemini already counts DRAM bytes once per multicast and L3 already forwards along the ring, so no DRAM reduction is possible in this model. |
Finding: at batch 16 the DRAM-bound share of run time grows, which caps what any D2D re-provisioning (and D2D-side mapping) can gain.
Bars: the selected HW. Table: mean on all three HW choices (per workload / group / ALL14; ALL14 excludes RNN). One HW per workload for batches 1/4/16. Diamonds: mean. Dashed lines: 10% (mean target), 20% (max target). Faded bars: provisional (oracle only).
Each design gets one identical mapping search (all variants, 3 DP modes, 20 rounds, seed 5) and is judged only by it, so search effort is equal across designs. Speedup vs uniform HW with the best of every mapping type. HW = ccw ring · middle · cw ring (B/cycle). Green = every batch ≥ 0%; the first row per workload is its best design.
Gemini models links by bandwidth only, so destination-to-destination multicast forwarding (L3) costs no extra time. Each model below re-selects both sides fairly (best mapping per side; common HW chosen with no slower batch). 4 chunks is the main evaluation model.
Best speedup of each batch on its own best K=2 HW (oracle), as methods are added. Missing levels: stage not run for that batch.
Workloads with results at more than one chiplet count. Common-HW per-batch speedup (final or provisional).